Rapid Design Space Exploration of a Reconfigurable Instruction-Set Processor
نویسندگان
چکیده
DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework Methodology for Rapid Accelerator Development Applied to Financial Applications A Reconfigurable Application Specific Instruction Set Processor. Adaptive processor architecture invited paperMichael Hübner, Diana Göhringer, Carsten Tradowsky, Jörg KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Cross-architectural design space exploration tool for reconfigurable Instruction trace compression for rapid instruction cache simulationAndhi.
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ورودعنوان ژورنال:
- IEICE Transactions
دوره 92-A شماره
صفحات -
تاریخ انتشار 2009